As the density of semiconductor integrated circuits increases, and the corresponding size of circuit elements decreases, circuit performance may be dominated by resistive-capacitance (RC) delay, for instance, between interconnect layers. RC delay may be reduced by decreasing the overall capacitance of an integrated circuit, and its components. As the size of technology nodes continues to decrease, it is desirable to reduce or minimize RC delay by customizing interlayer dielectrics used between, for instance, adjacent metal layers of an interconnect structure.